Target: Only use USART TX
RX is not required for our implementation since we've completely dropped the rootshell in favour of straight up UART vomiting. Signed-off-by: Patrick Pedersen <ctx.xda@gmail.com>
This commit is contained in:
16
README.md
16
README.md
@@ -120,21 +120,21 @@ Next, connect your Pi Pico to your target board as shown in the table below:
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| Pi Pico | STM32F1 |
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| ---------------- | --------- |
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| GND | GND |
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| GPIO0 / UART0_TX | USARTx_RX |
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| ~~GPIO0 / UART0_TX~~ **NO LONGER USED** | ~~USARTx_RX~~ **NO LONGER USED** |
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| GPIO1 / UART0_RX | USARTx_TX |
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| GPIO2 | VDD |
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| GPIO4 | NRST |
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| GPIO5 | BOOT0 |
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Where `USARTx_RX` and `USARTx_TX` are the `RX` and `TX` pins of the USART peripheral that will be used to dump the flash memory contents.
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Where `USARTx_TX` refers to the `TX` pin of a selected USART peripheral on the STM device, which will be utilized for transmitting the flash memory contents.
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The USART pins for STM32F1-series chips are assigned as follows:
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The USART TX pins for STM32F1-series chips are assigned as follows:
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| USART Peripheral | RX | TX |
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| ---------------- | ---- | ---- |
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| USART1 | PA10 | PA9 |
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| USART2 | PA3 | PA2 |
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| USART3 | PB11 | PB10 |
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| USART Peripheral | TX |
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| ---------------- | ---- |
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| USART1 | PA9 |
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| USART2 | PA2 |
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| USART3 | PB10 |
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Below is a picture that shows the hardware setup using a Blue Pill board as the target board with `USART1` used to dump the flash memory:
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24
dump.py
24
dump.py
@@ -100,17 +100,17 @@ def print_instructions():
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print(
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"2. Connect the Pi Pico to the STM32F1 target as follows (left Pico, right STM):"
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)
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print(" GND -> GND ")
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print(" 0 -> USARTx_RX")
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print(" 1 -> USARTx_TX")
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print(" 2 -> VDD ")
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print(" 4 -> NRST ")
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print(" 5 -> BOOT0 ")
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print(" GND -> GND ")
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print(" GPIO 0 -> NO LONGER USED (previously USARTx_RX)")
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print(" GPIO 1 -> USARTx_TX")
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print(" GPIO 2 -> VDD ")
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print(" GPIO 4 -> NRST ")
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print(" GPIO 5 -> BOOT0 ")
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print("")
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print("Where:")
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print(" USART1_RX = PA10, USART1_TX = PA9")
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print(" USART2_RX = PA3, USART2_TX = PA2")
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print(" USART3_RX = PB11, USART3_TX = PB10")
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print(" USART1_TX = PA9")
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print(" USART2_TX = PA2")
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print(" USART3_TX = PB10")
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print("")
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print("3. Follow further instructions provided by this script")
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print("For more detailed steps, see the README.md file.")
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@@ -456,9 +456,9 @@ if sram_entry_offset_supported(sram_entry_point) == False:
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# Select USART if not provided alreay
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if args.usart is None:
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print("Please select the USART used by the STM32F1 target to dump firmware")
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print("1: USART1 - RX: PA10 TX: PA9")
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print("2: USART2 - RX: PA3 TX: PA2")
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print("3: USART3 - RX: PB11 TX: PB10")
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print("1: USART1 - TX: PA9")
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print("2: USART2 - TX: PA2")
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print("3: USART3 - TX: PB10")
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print("Enter 1, 2 or 3: ", end="")
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while True:
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choice = input()
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Binary file not shown.
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Before Width: | Height: | Size: 345 KiB After Width: | Height: | Size: 347 KiB |
@@ -72,7 +72,7 @@ typedef struct __attribute__((packed))
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#define USART3 ((USART *)0x40004800u)
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#define USARTDIV 0x00000341u // 9600 baud @ 8Mhz
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#define USART_CR1_MSK 0x0000200Cu // 8-bit, no parity, enable RX/TX
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#define USART_CR1_MSK 0x00002008u // 8-bit, no parity, enable TX
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volatile USART *usart;
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@@ -90,10 +90,6 @@ USART *init_usart1()
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GPIOA->CRH &= ~(0xF << 4);
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GPIOA->CRH |= (PIN_CONFIG_ALT_PUSH_PULL << 4);
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// Set PA10 (RX) to input pull-up
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GPIOA->CRH &= ~(0xF << 8);
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GPIOA->CRH |= (PIN_CONFIG_INPUT_PULL_UP << 8);
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/* Configure and enable USART1 */
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USART1->BRR = USARTDIV;
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USART1->CR1 = USART_CR1_MSK;
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@@ -115,10 +111,6 @@ USART *init_usart2()
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GPIOA->CRL &= ~(0xF << 8);
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GPIOA->CRL |= (PIN_CONFIG_ALT_PUSH_PULL << 8);
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// Set PA3 (RX) to input pull-up
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GPIOA->CRL &= ~(0xF << 12);
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GPIOA->CRL |= (PIN_CONFIG_INPUT_PULL_UP << 12);
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/* Configure and enable USART2 */
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USART2->BRR = USARTDIV;
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USART2->CR1 = USART_CR1_MSK;
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@@ -138,10 +130,6 @@ USART *init_usart3()
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GPIOB->CRH &= ~(0xF << 8);
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GPIOB->CRH |= (PIN_CONFIG_ALT_PUSH_PULL << 8);
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// Set PB11 (RX) to input pull-up
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GPIOB->CRH &= ~(0xF << 12);
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GPIOB->CRH |= (PIN_CONFIG_INPUT_PULL_UP << 12);
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/* Configure and enable USART3 */
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USART3->BRR = USARTDIV;
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USART3->CR1 = USART_CR1_MSK;
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